[AK4492]
Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
tB
tBL
tBH
tBW
tWCK
tWB
tWCKL
tWCKH
tDH
27
10
10
5
1.3
5
54
54
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
usec
nsec
nsec
nsec
nsec
nsec
BCK Pulse Width Low
BCK Pulse Width High
BCK “” to WCK Edge
WCK Period
WCK Edge to BCK “”
WCK Pulse Width Low
WCK Pulse Width High
DINL/R Hold Time
tDS
5
DINL/R Setup Time
DSD Audio Interface Timing
Sampling Frequency
fs
30
48
kHz
(64fs mode, DSDSEL [1:0] bits = “00”)
DCLK Period
-
tDCK
tDCKL
tDCKH
tDDD
1/64fs
-
-
-
nsec
nsec
nsec
nsec
144
144
20
-
-
-
DCLK Pulse Width Low
DCLK Pulse Width High
20
DCLK Edge to DSDL/R
(Note 43)
(128fs mode, DSDSEL [1:0] bits = “01”)
DCLK Period
-
tDCK
tDCKL
tDCKH
tDDD
1/128fs
-
-
-
nsec
nsec
nsec
nsec
72
72
10
DCLK Pulse Width Low
DCLK Pulse Width High
-
-
-
DCLK Edge to DSDL/R
(Note 43)
10
(256fs mode, DSDSEL [1:0] bits = “10”)
DCLK Period
-
tDCK
tDCKL
tDCKH
tDDD
1/256fs
-
-
-
nsec
nsec
nsec
nsec
36
36
5
DCLK Pulse Width Low
DCLK Pulse Width High
-
-
-
DCLK Edge to DSDL/R
(Note 43)
5
Note 43. DSD data transmitting device must meet this time. “tDDD” is defined from DCLK “↓” until
DSDL/R edge when DCKB bit = “0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R
edge when DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is
defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
016011073-E-00
2016/12
- 29 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
