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AK4492ECB 参数 Datasheet PDF下载

AK4492ECB图片预览
型号: AK4492ECB
PDF下载: 下载PDF文件 查看货源
内容描述: [Quality Oriented 32-Bit 2ch DAC]
分类和应用:
文件页数/大小: 101 页 / 2100 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4492]  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
PCM Audio Interface Timing  
Normal Mode (TDM[1:0] bits = “00”)  
BICK Period  
Normal Speed Mode  
Double Speed Mode  
Quad Speed Mode  
Oct speed mode  
Hex speed mode  
tBCK  
tBCK  
tBCK  
tBCK  
tBCK  
tBCKL  
tBCKH  
tBLR  
1/256fsn  
1/128fsd  
1/64fsq  
1/64fso  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
1/64fsh  
BICK Pulse Width Low  
BICK Pulse Width High  
BICK “” to LRCK Edge  
LRCK Edge to BICK “”  
SDATA Hold Time  
9
9
5
5
5
5
(Note 39)  
(Note 39)  
tLRB  
tSDH  
tSDS  
SDATA Setup Time  
TDM128 mode (TDM[1:0] bits = “01”)  
BICK Period  
Normal Speed Mode  
Double Speed Mode  
Quad Speed Mode  
tBCK  
tBCK  
tBCK  
tBCKL  
tBCKH  
tBLR  
tLRB  
tSDH  
tSDS  
1/128fsn  
1/128fsd  
1/128fsq  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
BICK Pulse Width Low  
BICK Pulse Width High  
BICK “” to LRCK Edge  
LRCK Edge to BICK “”  
SDATA Hold Time  
14  
14  
14  
14  
5
(Note 39)  
(Note 39)  
5
SDATA Setup Time  
TDM256 mode (TDM[1:0] bits = “10”)  
BICK Period  
Normal Speed Mode  
tBCK  
tBCK  
tBCKL  
tBCKH  
tBLR  
1/256fsn  
1/256fsd  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
Double Speed Mode  
BICK Pulse Width Low  
BICK Pulse Width High  
BICK “” to LRCK Edge  
LRCK Edge to BICK “”  
TDMO Setup time BICK ”  
TDMO Hold time BICK “”  
SDATA Hold Time  
(Note 40)  
14  
14  
14  
14  
5
5
5
5
(Note 39)  
(Note 39)  
tLRB  
tBSS  
tBSH  
tSDH  
tSDS  
(Note 42)  
SDATA Setup Time  
TDM512 mode (TDM[1:0] bits = “11”)  
BICK Period  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Normal Speed Mode  
BICK Pulse Width Low  
BICK Pulse Width High  
BICK “” to LRCK Edge  
LRCK Edge to BICK “”  
TDMO Setup time BICK ”  
TDMO Hold time BICK ”  
SDATA Hold Time  
(Note 41)  
tBCK  
tBCKL  
tBCKH  
tBLR  
1/512fsn  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
14  
14  
14  
14  
5
5
5
5
(Note 39)  
(Note 39)  
tLRB  
tBSS  
tBSH  
tSDH  
tSDS  
(Note 42)  
SDATA Setup Time  
Note 39. BICK rising edge must not occur at the same time as LRCK edge.  
Note 40. Daisy Chain Mode, fsd (max) = 96 kHz if “TVDD < 3.0V”.  
Note 41. Daisy Chain Mode, fsn (max) = 48 kHz if “TVDD < 3.0V”.  
Note 42. LDOE pin = “L”, tBSH (min) = 4 nsec if “TVDD > 2.6V”.  
016011073-E-00  
2016/12  
- 28 -  
 
 
 
 
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