[AK4492]
■ Switching Characteristics
(Ta = -40 ~ 85 C; VDDL/R = 4.755.25 V, AVDD = TVDD = 1.73.6V, DVDD = 1.7~1.98 V, CL = 20 pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
-
-
-
-
MHz
%
nsec
nsec
49.152
60
-
-
LRCK Clock Timing (Note 37)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
fsn
fsd
fsq
fso
fsh
8
54
108
-
-
45
-
-
-
54
108
216
-
-
55
kHz
kHz
kHz
kHz
kHz
%
384
768
-
Hex speed mode
Duty Cycle
Duty
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
fsn
fsd
fsq
tLRH
tLRL
8
54
108
1/128fs
1/128fs
-
-
-
-
-
54
108
216
-
kHz
kHz
kHz
nsec
nsec
Low time
-
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
fsn
fsd
tLRH
tLRL
8
54
1/256fs
1/256fs
-
-
-
-
54
108
-
-
kHz
kHz
nsec
nsec
Low time
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
fsn
tLRH
tLRL
8
-
-
-
54
-
-
kHz
nsec
nsec
1/512fs
1/512fs
Low time
Note 37. The MCLK frequency must be changed while the AK4492 is in reset state by setting the PDN pin
= “L” or RSTN bit = “0”.
016011073-E-00
2016/12
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
