[AK4480]
Analog Ground
Digital Ground
1
2
SMUTE/CSN
LRCK 30
SDATA 29
BICK 28
SD/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0/CAD1
DIF1/DZFL
DIF2
3
4
PDN
27
5
DVDD 26
VSS4 25
MCLK 24
AVDD 23
System
Controller
6
7
AK4480
8
PSN
ACKS/DZFR
9
VSS3 22
AOUTRP
10
AOUTLP 21
11 AOUTRN
12 VSS1
AOUTLN 20
VSS2
19
VDRR
13
14
VDDL 18
VREFHL 17
VREFLL 16
VREFHR
15 VREFLR
Figure 18. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD
respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from regulators with keeping low
impedance. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be connected
to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to
the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency
noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4480.
3. Analog Outputs
The analog outputs are full differential outputs and 2.4Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around
AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−.
If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.
MS1146-E-03
2012/01
- 39 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
