[AK4480]
[3] External Digital Filter Mode (EX DF I/F Mode)
DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL
and DINR pins. Three formats are available (Table 16) by DIF2-0 bits setting. The data is latched on the rising edge of
BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each
sampling speed are shown in Table 15.
Sampling
Speed[kHz]
WCK
MCLK&BCK [MHz]
ECS
128fs
N/A
192fs
N/A
256fs
N/A
384fs
N/A
512fs
22.5792
32
768fs
33.8688
48
16fs
DW
8fs
44.1(30~54)
44.1(30~54)
96(54~108)
96(54~108)
0
1
0
1
(default)
16.9344
48
33.8688
N/A
N/A
N/A
N/A
11.2896
32
N/A
96
DW
24.576
32
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
8fs
DW
4fs
DW
4fs
48
18.432
48
36.864
96
12.288
32
N/A
24.576
32
N/A
36.864
N/A
N/A
N/A
192(108~216)
192(108~216)
0
1
48
36.864
96
DW
2fs
DW
N/A
Table 15. System Clock Example (EX DF I/F mode) (N/A: Not available)
Mode
DIF2
DIF1
DIF0
Input Format
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16bit LSB justified
N/A
N/A
N/A
24bit LSB justified
32bit LSB justified (default)
N/A
N/A
Table 16. Audio Interface Format (EX DF I/F mode) (N/A: Not available)
MS1146-E-03
2012/01
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
