[AK4480]
MCLK= 256fs/384fs supports sampling rate of 32kHz ~ 96kHz (Table 12). However, when the sampling rate is 32kHz ~
48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS bit
MCLK
256fs/384fs/512fs/768fs
256fs/384fs
DR,S/N
114dB
111dB
114dB
0
1
1
512fs/768fs
Table 12. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)
[2] DSD Mode
The external clocks, which are required to operate the AK4480, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4480 is automatically placed in reset state when MCLK is stopped during a normal operation, and the analog
output becomes AVDD/2 (typ).
DCKS bit
MCLK Frequency
512fs
DCLK Frequency
0
1
64fs
64fs
(default)
768fs
Table 13. System Clock (DSD Mode)
MS1146-E-03
2012/01
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AKM [ ASAHI KASEI MICROSYSTEMS ]
