[AK4480]
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31 30
12 11 10
0
9
31 30
12 11 10
0
9
31
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
1
BICK(64fs)
SDATA
8
1
0
31 30
20 19 18
8
1
0
31
31 30
20 19 18
Lch Data
Rch Data
31: MSB, 0:LSB
Figure 6. Mode 6 Timing
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
0
1
BICK(128fs)
SDATA
31
31
13 12 11
0
9
31
13 12 11
0
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDATA
0
21 20 19
8
2
1
0
31
21 20 19
Rch Data
9
8
2
1
0
Lch Data
31: MSB, 0:LSB
Figure 7. Mode 7 Timing
[2] DSD Mode
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
D0
D1
D2
D3
D3
DSDL,DSDR
Phase Modulation
D1
D2
D1
D2
Figure 8. DSD Mode Timing
MS1146-E-03
2012/01
- 23 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
