[AK4480]
OPERATION OVERVIEW
■ D/A Conversion Mode
In serial mode, the AK4480 can covert both PCM and DSD data. The D/P bit controls PCM/DSD mode. When DSD
mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK,
LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4480 should be reset by RSTN bit. It takes
about 2/fs ~ 3/fs to change the mode. In parallel mode, the AK4480 can only convert PCM data.
D/P bit
Interface
PCM
DSD
0
1
Table 1. PCM/DSD Mode Control
When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter
(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXD bit controls the modes. When
switching internal and external digital filters, the AK4480 must be reset by RSTN bit. A Digital filter switching takes
2~3k/fs.
Ex DF bit
Interface
PCM
EX DF I/F
0
1
Table 2. Digital Filter Control (DP bit = “0”)
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4480, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. There are two modes for setting MCLK frequency, Manual Setting Mode and Auto Setting Mode.
In auto setting mode, sampling speed and MCLK frequency are detected automatically and then the initial master clock is
set to the appropriate frequency (Table 3). When external clocks are changed, the AK4480 should be reset by the PDN pin
or RSTN bit.
The AK4480 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation
mode, and the analog output goes to AVDD/2 (typ). When MCLK and LRCK are input again, the AK4480 is powered up.
After exiting reset following power-up, the AK4480 is not fully operational until MCLK and LRCK are input.
The MCLK frequency corresponding to each sampling speed should be provided (Table 3).
(1) Parallel Mode (P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. Quad
speed mode is not supported in this mode.
MS1146-E-03
2012/01
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
