[AK4424]
OPERATION OVERVIEW
■
System Clock
The external clocks required to operate the AK4424 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the internal master
clock is set to the appropriate frequency (Table
1).
The AK4424 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,
and the analog output is forced to 0V(typ). When MCLK and LRCK are input again, the AK4424 is powered up. After
power-up, the AK4424 is in the power-down mode until MCLK and LRCK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
256fs
384fs
512fs
-
-
16.3840
-
-
22.5792
-
-
24.5760
8.192
12.288
11.2896
16.9344
12.288
18.432
22.5792
33.8688
-
24.5760
36.8640
-
-
-
-
-
-
-
Table 1. system clock example
Sampling
Speed
Normal
128fs
-
-
-
192fs
-
-
-
768fs
24.5760
33.8688
36.8640
1152fs
36.8640
-
-
Double
-
-
-
-
-
-
-
-
-
-
22.5792
24.5760
-
-
33.8688
36.8640
Quad
When MCLK= 256fs/384fs, the AK4424 supports sampling rate of 32kHz~96kHz (Table
1).
But, when the sampling rate
is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. (Table
2)
MCLK
DR,S/N
256fs/384fs
102dB
512fs/768fs
105dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■
Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The AK4424 supports I
2
S format as
shown in
The serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. It
can be used for 16/20 bit I
2
S formats by zeroing the unused LSBs.
SDTI Format
BICK
2
24bit I S
≥48fs
Table 3. Audio Data Format
Figure
MS0935-E-03
-9-
2010/09
AKM [ ASAHI KASEI MICROSYSTEMS ]
