[AK4424]
■ System Reset
The AK4424 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4424 is in power-down mode until LRCK are input.
Power Supply
(VDD, CVDD)
(6)
Low
MCLK
20 us
Analog
Circuit
(1)
Power down
Power-up
2, 3
LRCK
Digital
(2)
Power down
Power down
Power-up
Power-up
Time A
Circuit
Charge Pump
Circuit
(3)
Charge Pump
Counter circuit
D/A In
(Digital)
“0” data
MUTE (D/A Out)
D/A Out
(Analog)
(4)
(5)
DZF
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8) : Double speed mode
Time A = 1024/ (fs x 4) : Quadruple speed mode
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at a different timing from this figure.
Figure 7. System reset diagram
MS0935-E-03
2010/09
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
