[AK4424]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
23:MSB, 0:LSB
Don’t care
23 22
1
0
Don’t care
23
Lch Data
Figure 3. Audio Interface Timing
Rch Data
De-emphasis Filter
The AK4424 integrates digital de-emphasis filter (tc = 50/15µs). The DEM pin which enables the digital de-emphasis
filter by setting “H” is internal pull-down pin. Refer to the section of “FILTER CHARACTERISTICS” regarding the gain
error when the de-emphasis filter is enabled. In case of double speed mode (MCLK=256fs/384fs) and quad speed mode
(MCLK=128fs/192fs), the digital de-emphasis filter is always off.
DEM pin
De-emphasis Filter
1
0
ON
(default)
OFF
Table 4. De-emphasis Filter Control (Normal Speed Mode)
■ Zero detect function
When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. If the
input data of Lch and Rch are continuously not zeros orderly, or if each Rch or Lch is continuously not zeros, the DZF pin
immediately returns to “L”.
MS0935-E-03
2010/09
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
