[AK4424]
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission. In one cycle of LRCK, eight “H” pulses or more
must not be input to the SMUTE pin.
SMUTE pin
1024/fs
(1)
1024/fs
0dB
(3)
Attenuation
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF pin
Notes:
(1) The time for input data attenuation to -∞, is
Normal Speed Mode: 1024 LRCK cycles (1024/fs).
Double Speed Mode: 2048 LRCK cycles (2048/fs).
Quad Speed Mode : 4096 LRCK cycles (4096/fs).
(2) The analog output corresponding to a specific digital input has a group delay, GD.
(3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level in the same cycle.
(4) When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. The
DZF pin immediately returns to “L” if the input data are not zero.
Figure 6. Soft Mute and Zero detect function
MS0935-E-03
2010/09
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
