[AK4372]
2) DAC → Lineout
Power Supply
PDN pin
(1) >150ns
(2)
>0s
PMVCM bit
Clock Input
PMDAC bit
Don’t care
Don’t care
(5)
Don’t care
(4) >0s
DAC Internal
State
PD(Power-down)
(3) >0s
Normal Operation
PD
Normal Operation
SDTI pin
DALL,
DARR bits
PMLO bit
ATTL/R7-0 bits
00H(MUTE)
10H(MUTE)
FFH(0dB)
00H(MUTE)
0FH(0dB)
FFH(0dB)
LMUTE,
ATTS3-0 bits
(7) (8)
(7) (8)
(7) GD (8) 1061/fs
(6)
(6)
(6)
LOUT/ROUT pins
(Hi-Z)
(Hi-Z)
Figure 29. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”.
(3) DALL and DARR bits should be changed to “1” after the PMVCM bit is changed to “1”.
(4) PMDAC and PMLO bits should be changed to “1” after DALL and DARR bits is changed to “1”.
(5) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The LOUT/ROUT buffer can operate without these clocks.
(6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(7) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(8) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0684-E-02
2008/12
- 36 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
