[AK4372]
2) DAC → Lineout
Power Supply
PDN pin
(1) >150ns
(2)>0s
Don’t care
Don’t care
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
(4) ~20ms
Unstable
MCKO pin
Don’t care
Unstable (5)
Unstable
Unstable (5)
Unstable
BICK, LRCK pins
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
Unstable
Don’t care
Unstable
SDTI pin
DALL,
DARR bits
(6) >0s
(6) >0s
(7) >0s
(7) >0s
PMLO bit
ATTL/R7-0 bits
00H(MUTE)
FFH(0dB)
00H(MUTE)
0FH(0dB)
FFH(0dB)
LMUTE,
ATTS3-0 bits
10H(MUTE)
(9) GD (10) 1061/fs (9) (10)
(9) (10)
(8)
(8)
(8)
LOUT/ROUT pins
(Hi-Z)
(Hi-Z)
Figure 33. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to Table 4. After the PLL is locked, the MCKO pin outputs the master clock.
(5) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these
clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks.
(6) DALL and DARR bits should be changed to “1” after the PLL is locked
(7) PMLO bit is changed to “1”.
(8) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(9) Analog output corresponding to the digital input has group delay (GD) of 22fs(=499μs@fs=44.1kHz).
(10)The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0684-E-02
2008/12
- 40 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
