[AK4372]
Power-Up/Down Sequence (PLL Slave mode)
1) DAC → HP-Amp
(12)
Power Supply
PDN pin
(1)
>150ns
Don’t care
Don’t care
(2) >0s
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Unstable
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
(4) ~20ms
MCKO pin
Don’t care
(5)
Unstable (5)
Unstable
Don’t care
BICK,
LRCK pins
Unstable
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
PD
Don’t care
Don’t care
Unstable
SDTI pin
Unstable
DALHL,
DARHR bits
(6) >0s
(6) >0s
PMHPL,
PMHPR bits
(7) >2ms
(7) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
FFH(0dB)
(10)
FFH(0dB)
00H(MUTE)
00H(MUTE)
(9)
00H(MUTE)
(11)
(11) (10)
(10) GD (11) 1061/fs (10) (11)
(9)
(8)
(8)
HPL/R pin
Figure 32. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to Table 4. After the PLL is locked, the MCKO pin outputs the master clock.
(5) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these
clocks can be stopped. The headphone-amp can operate without these clocks.
(6) DALHL and DARHR bits should be changed to “1” after the PLL is locked.
(7) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after the DALHL and DARHR bits are changed to “1”.
(8) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ).
(9) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the
DALHL/DARHR bits should be changed to “0”.
(10)Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(11)The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(12)The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or after AVDD.
MS0684-E-02
2008/12
- 39 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
