[AK4372]
■ Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DALL, LINL, RINL and MINL bits control each path switch of LOUT. DARR, LINR, RINR and
MINR bits control each path switch of ROUT. When LM bit = “0”, LOG bit = “0” (R1L = R2L = RDL = 100k) and ATTS3-0
bits is “0FH”(0dB), the mixing gain is 0dB(typ) for all paths. When the LOG bit = “1”(RDL= 50k), the DAC path gain is
+6dB. When LM bit = “1”, LIN and RIN signals are output from LOUT/ROUT pins as (L+R)/2 respectively.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 51 shows the external bias circuit example.
R1L
LIN pin
LINL bit
R1L
RIN pin
RINL bit
R2L
100k(typ)
MIN pin
RL
MINL bit
DALL bit
RDL
RL
DAC Lch
−
+
−
+
LOUT pin
R1L
R1L
R2L
LIN pin
RIN pin
MIN pin
LINR bit
RINR bit
MINR bit
DARR bit
100k(typ)
RL
RDL
RL
DAC Rch
−
−
+
ROUT pin
+
Figure 26. Summation circuit for stereo line output
MS0684-E-02
2008/12
- 33 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
