[AK4372]
■ Power-Up/Down Sequence (EXT mode)
1) DAC → HP-Amp
(10)
Power Supply
PDN pin
(1)
>150ns
Don’t care
Don’t care
(2) >0s
PMVCM bit
Clock Input
PMDAC bit
Don’t care (3)
Don’t care
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
PD
SDTI pin
DALHL,
DARHR bits
(4) >0s
(4) >0s
PMHPL,
PMHPR bits
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
FFH(0dB)
(8)
00H(MUTE)
FFH(0dB)
00H(MUTE)
00H(MUTE)
(9)
(8)
(8)
(9)
(8) GD
(9) 1061/fs
(9)
(6)
(6)
(7)
(7)
HPL/R pin
Figure 28. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM and PMDAC bits should be changed to “1” after the PDN pin is set to “H”.
(3) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The headphone-amp can operate without these clocks.
(4) DALHL and DARHR bits should be changed to “1” after PMVCM and PMDAC bit is changed to “1”.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2μF) after the DALHL and DARHR bits are changed to “1”
(6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ).
(7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after the HPL and HPR pins settle to VSS1. After that, the
DALHL and DARHR bits should be changed to “0”.
(8) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µs@fs=44.1kHz).
(9) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(10)The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or later than
AVDD.
MS0684-E-02
2008/12
- 35 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
