ASAHI KASEI
[AK4367]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4367 supports the standard-mode I2C-bus (max: 100kHz). The AK4367 does not support a fast-mode I2C-bus
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 22 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 28). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0
(device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0
pins) set these device address bits (Figure 23). If the slave address matches that of the AK4367, the AK4367 generates an
acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 29). A R/W bit value of “1” indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4367. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 24). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 25). The AK4367 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 28).
The AK4367 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4367
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 08H prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 30) except for the START and STOP
conditions.
S
S
T
O
P
T
A
R
T
R/W="0"
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 22. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
0
CAD0
R/W
(Those CAD0 should match with CAD0 pin)
Figure 23. The First Byte
0
0
0
A4
A3
A2
A1
D1
A0
D0
Figure 24. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 25. Byte Structure after the second byte
MS0247-E-02
2005/10
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AKM [ ASAHI KASEI MICROSYSTEMS ]
