ASAHI KASEI
[AK4367]
4) LIN/RIN/MIN → MOUT
Power Supply
PDN pin
(1) >150ns
(2) >0
PMVCM bit
Don’t care
LINM, RINM, MINM bit
MUTEN bit
(3) >0
(5) >2ms
(5) >0
PMMO bit
(4)
(Hi-Z)
LIN/RIN/MIN pin
MMUTE,
(Hi-Z)
10H(MUTE)
(Hi-Z)
0FH(0dB)
ATTM3-0 bit
(6)
(6) (Hi-Z)
(6)
MOUT pin
Figure 20. Power-up/down sequence of LIN/RIN/MIN and MOUT
(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stopped
when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.
(3) LINM, RINM and MINM bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINM, RINM or MINM bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage.
(5) MUTEN and PMMO bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2µF)
after LINM, RINM and MINM bits are changed to “1”.
(6) When PMMO bit is changed, pop noise is output from MOUT pin.
MS0247-E-02
2005/10
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
