ASAHI KASEI
[AK4367]
3) LIN/RIN/MIN → HP-amp
Power Supply
(1) >150ns
PDN pin
(2) >0
PMVCM bit
Don’t care
(3) >0
LINL, MINL,RINR, MINR bit
PMHPL/R bit
(5) >2ms
(5) >0
MUTEN bit
(Hi-Z)
(4)
LIN/RIN/MIN pin
HPL/R pin
(Hi-Z)
(7)
(6)
(6)
Figure 19. Power-up/down sequence of LIN/RIN/MIN and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stopped
when DAC is not used.
(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.
(3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”.
(4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage.
(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2µF) after LINL, MINL, RINR and MINR bits are changed to “1”.
(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is
tr = 100k x C(typ). When C=1µF, time constant is 100ms(typ).
(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is tf =
200k x C(typ). When C=1µF, time constant is 200ms(typ).
PMHPL, PMHPR, LINL, MINL, RINR and MINR bits should be changed to “0” after HPL and HPR pins go to VSS.
MS0247-E-02
2005/10
- 23 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
