ASAHI KASEI
[AK4367]
2) DAC → MOUT
Power Supply
PDN pin
(1) >150ns
(2)
>0
PMVCM bit
Clock Input
PMDAC bit
Don’t care
Don’t care
(5)
Don’t care
(4) >0
DAC Internal
State
PD(Power-down)
Normal Operation
PD
Normal Operation
SDTI pin
DACM bit
PMMO bit
(3) >0
ATTL/R7-0 bit
00H(MUTE)
FFH(0dB)
00H(MUTE)
0FH(0dB)
FFH(0dB)
MMUTE,
ATTM3-0 bit
10H(MUTE)
(Hi-Z)
(7) (8)
(7) (8)
(7) GD (8) 1061/fs
(6)
(6)
(6)
MOUT pin
(Hi-Z)
Figure 18. Power-up/down sequence of DAC and MOUT
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.
(3) DACM bit should be changed to “1” after PMVCM bit is changed to “1”.
(4) PMDAC and PMMO bits should be changed to “1” after DACM bit is changed to “1”.
(5) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be
stopped. MOUT buffer can operate without these clocks.
(6) When PMMO bit is changed, pop noise is output from MOUT pin.
(7) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µs@fs=44.1kHz).
(8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
MS0247-E-02
2005/10
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
