[AK4129]
When the AK4129 is in master mode, SDTI1-3 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode
(Table 2). The SDTI1-3 output data are output by the ILRCK1 and IBICK1 clocks in a format shown in Table 6 and Table
7. The ILRCK1 clock bypasses the SRC and it is output from the OLRCK pin. The IBICK1 clock bypasses the SRC and it
is output from the OBICK pin.
OLRCK(O)
OBICK(O)
Bypass
SRC1
SRC2
SRC3
Input
Serial
Audio
I/F
IBICK1
ILRCK1
SDTI1
SMUTE
Dither
+
SDTO1
DEM
DEM
DEM
FIR
FIR
FIR
SRC
SRC
SRC
SRC
OBIT1
OBIT2
0.5 LSB
ODIF1
ODIF0
Bypass
Input
Serial
Audio
I/F
IBICK2
ILRCK2
SDTI2
SMUTE
Dither
Output
Serial
Audio
I/F
+
SDTO2
SDTO3
SRC
0.5 LSB
Bypass
Input
Serial
Audio
I/F
IBICK3
ILRCK3
SDTI3
SMUTE
Dither
+
SRC
0.5 LSB
Internal
OSC
IMCLK
PDN
PM1
PM2
UNLOCK
MCKO
Bypass
uP
I/F
X'tal
Osc
Clock
Div
Internal
Regulator
SRC
AVDD
VSS1
.
REF
CM2 CM1 CM0
SDA SCL
OMCLK/XTI
CAD0
XTO
VD18
SPB
Figure 24. Bypass Mode in Master Mode (Synchronous mode INAS pin = “L”)
MS1173-E-01
2010/09
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
