[AK4129]
■ System Clock for Output PORT
The output ports work in master mode and slave mode. The CM2-0 pins select the master/slave mode.
CM2 CM1 CM0
OMCLK/XTI
Input
FSO with
X’tal
Mode
Master / Slave
MCKO Output
FSO
pin
pin
pin
0
1
2
3
L
L
L
L
L
L
H
H
L
H
L
Master
Master
Master
Master
256FSO
384FSO
512FSO
768FSO
256FSO
384FSO
512FSO
44.1~96kHz
29.4~64kHz
22.05~48kHz
14.7~32kHz
8k∼108kHz
8k∼96kHz
8k∼54kHz
8k∼48kHz
H
768FSO
OMCLK Input
Clock
128FSO
IMCLK Input
Clock
4
H
L
L
Slave
Not used (Note 24)
128FSO (Note 25)
Not used (Note 24)
-
8k∼216kHz
8k∼216kHz
8k∼216kHz
5
6
7
H
H
H
L
H
H
H
L
H
Master
Slave(Bypass)
Master(Bypass)
88.2~192kHz
-
Note 24. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs “L” if the OMCLK/XTI pin is
connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the
MCKO pin. In Mode 6-7, OMCLK/XTI input is ignored internally.
Note 25. Output ports do not support TDM mode in this mode.
Table 3. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “L”)
In serial control mode (SPB pin = “H”), the BYPS bit selects SRC bypass mode and SRC mode.
The default value of the BYPS bit is “0” (SRC mode).
CM2 CM1 CM0 BYPS
OMCLK/XTI
Input
MCKO
Output
FSO with
X’tal
Mode
Master / Slave
FSO
pin
pin
pin
bit
0
1
2
3
L
L
L
L
L
L
H
H
L
H
L
0
0
0
0
Master
Master
Master
Master
256FSO
384FSO
512FSO
768FSO
256FSO
384FSO
512FSO
768FSO
OMCLK
Input
44.1~96kHz
29.4~64kHz
22.05~48kHz
14.7~32kHz
8∼108kHz
8∼96kHz
8∼54kHz
8k~48kHz
H
Not used (Note 26)
128FSO (Note 25)
4
H
L
L
0
Slave
-
8∼216kHz
8∼216kHz
Clock
128FSO
5
6
7
8
9
10
11
12
13
14
15
H
H
H
L
L
L
L
H
H
L
H
L
H
L
H
L
H
L
0
0
0
1
1
1
1
1
1
1
1
Master
88.2~192kHz
Slave (Bypass)
Master (Bypass)
Master (Bypass)
Master (Bypass)
Master (Bypass)
Master (Bypass)
Slave (Bypass)
Master (Bypass)
Slave (Bypass)
Master (Bypass)
L
IMCLK
Input
Clock
H
H
L
L
H
H
Not used (Note 26)
-
8∼216kHz
L
H
H
H
H
H
L
H
Note 26. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs “L” if the OMCLK/XTI pin is
connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the
MCKO pin. In Mode 6-15, OMCLK/XTI input is ignored internally.
Table 4. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “H”)
MS1173-E-01
2010/09
- 23 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
