[AK4129]
• Stereo Mode and Slave Mode
1/FSO
VIH
VIL
OLRCK(I)
tLRCH
tLRCL
Duty
= tLRCH (or tLRCL) x FSO x 100
tBCK
VIH
OBICK(I)
VIL
tBCKH
tBCKL
• TDM256 Mode and Slave Mode
1/FSO
VIH
VIL
OLRCK(I)
tLRH
tLRL
tBCK
VIH
VIL
OBICK(I)
tBCKH
tBCKL
Figure 7. OLRCK, OBICK, Clock Timing (Slave Mode)
• Stereo Mode and Master Mode
1/FSO
50%DVDD
OLRCK(O)
tLRCH
tLRCL
Duty
= tLRCH (or tLRCL) x FSO x 100
1/ fBCK
OBICK(O)
50%DVDD
tBICKH
tBICKL
dBCK
= tBICKH(or tBICKL) x fBCK x 100
• TDM256 Mode and Master Mode
1/FSO
50%DVDD
OLRCK(O)
24bit MSB justified
tLRH
1/FSO
50%DVDD
OLRCK(O)
24bit I2S
tLRL
1/ fBCK
OBICK(O)
50%DVDD
tBICKH
tBICKL
dBCK
= tBICKH(or tBICKL) x fBCK x 100
Figure 8. OLRCK, OBICK, Clock Timing (Master Mode)
MS1173-E-01
2010/09
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
