[AK4129]
Units
Parameter
Control Interface Timing (I2C Bus):
Symbol
min
typ
max
-
1.3
0.6
400
-
-
kHz
μs
μs
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
fSCL
tBUF
tHD:STA
(prior to first clock pulse)
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
-
-
-
-
0.3
0.3
-
μs
μs
μs
μs
μs
μs
μs
μs
ns
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
tF
tSU:STO
tSP
50
Suppressed by Input Filter
pF
Capacitive load on bus
Cb
-
400
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1173-E-01
2010/09
- 15 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
