[AK4129]
■ Timing Diagram
1/fECLK
VIH
VIL
IMCLK(I)
tECLKH
tECLKL
dECLK
= tECLKH (or tECLKL) x fECLK x 100
1/fCLK
VIH
VIL
OMCLK(I)
tCLKH
tCLKL
1/fMCK
MCKO(O)
50%DVDD
tMCKH
tMCKL
dMCLK
= tMCKH (or tMCKL) x fMCK x 100
Figure 5. IMCLK, OMCLK, MCKO Clock Timing
•Stereo Mode and Slave Mode
1/FSI
VIH
VIL
LRCK1-3(I)
tLRCH
tLRCL
Duty
= tLRCH (or tLRCL) x FSI x 100
tBCK
VIH
IBICK1-3(I)
VIL
tBCKH
tBCKL
•TDM256 Mode and Slave Mode
1/FSI
VIH
VIL
LRCK1(I)
tLRH
tLRL
tBCK
VIH
VIL
IBICK1(I)
tBCKH
tBCKL
Figure 6. ILRCK1-3, IBICK1-3 Clock Timing
MS1173-E-01
2010/09
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