[AK4129]
Output PORT (TDM256 slave mode)
OBICK Period
OBICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
81
32
32
20
20
ns
ns
ns
ns
ns
ns
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OBICK “↓” to SDTO1
(Note 17)
(Note 17)
20
Output PORT (Stereo Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO1-3
fBCK
dBCK
tMBLR
tBSD
64 FSO
50
Hz
%
ns
ns
−20
−20
20
20
Output PORT (TDM256 master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO1
fBCK
dBCK
tMBLR
tBSD
-
-
256 FSO
50(Note 19)
-
-
-
10
20
Hz
%
ns
ns
−10
−20
Reset Timing
PDN Pulse Width
(Note 18)
tPD
150
ns
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. The AK4129 can be reset by bringing the PDN pin = “L”.
Note 19. When OMCLK=512FSO. If the OMCLK=256FSO, OMCLK clock is though and output from the OBICK pin.
When OMCLK = 384FSO, dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%] or (tCLKL)/(tCLKL+1/fCLK) x100
[%]. When OMCLK=768FSO, dBCK= (1/fCLK)/(3/fCLK) x100 [%].
OMCLK=384FSO
1/fCLK
1/fCLK
tCLKH
tCLKH
OMCLK pin
tCLKL
tCLKL
tCLKL
OBICK pin Ouput
(TDM256
Master mode)
1/fCLK
1/fCLK
OMCLK=768FSO
1/fCLK
1/fCLK
1/fCLK
OMCLK pin
1/fCLK
OBICK pin Output
(TDM256
Master mode)
3/fCLK
3/fCLK
MS1173-E-01
2010/09
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
