[AK4129]
IDIF2
Pin
IDIF1
Pin
IDIF0
Pin
ILRCK
1-3
IBICK
1-3
IBICK1-3
Mode
SDTI1-3 Format
Freq
(Note 23) (Note 23) (Note 23)
0
1
2
L
L
L
L
L
H
L
H
L
16bit, LSB justified
20bit, LSB justified
≥ 32FSI
≥ 40FSI
≥ 48FSI
≥ 48FSI
32FSI
≥ 48FSI
256FSI
256FSI
24bit, MSB justified
24/16bit, I2S Compatible
16bit, I2S Compatible
24bit, LSB justified
Input
Input
3
L
H
H
4
5
6
H
H
H
L
L
H
L
H
X
TDM 24bit, MSB justified
TDM 24bit, I2S Compatible
Table 2. Input PORT Audio Interface Format (Parallel Control Mode, SPB pin= “L”) (X: Don’t care)
Note 23. In serial control mode (SPB pin = “H”), setting of IDIF2-0 pins is ignored. IDIF[12:10] bits setting is reflected to
SRC1, IDIF[22:20] bits setting is reflected to SRC2, and IDIF[32:30] bits setting is reflected to SRC3.
ILRCK
0
1
2
3
9 10 11 12 13 14 15 0
1
2
3
9 10 11 12 13 14 15 0 1
IBICK(32fs)
SDTI(i)
15 14 13
7
6
5
4
3
2
1
0 15 14 13
7
6
5
4
3
2
2
1
0 15
0
1
2
3
17 18 19 20
31 0
1
2
3
17 18 19 20
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care 15 14 13 12
15:MSB, 0:LSB
1
0
Don't Care 15 14 13 12
Rch Data
1 0
Lch Data
Figure 14. Mode 0 Timing (16bit, LSB justified)
ILRCK
0
1
2
12 13
24
31 0
1
2
12 13
24
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care 19
19:MSB, 0:LSB
8
1
0
Don't Care 19
8
1
0
Lch Data
Rch Data
Figure 15. Mode 1 Timing (20bit, LSB justified)
ILRCK
0
1
2
20 21 22 23 24
31 0
1
2
20 21 22 23 24
31 0
1
IBICK(64fs)
SDTI(i)
23 22
4
3
2
1
0
Don't Care 23 22
4
3
2
1
0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 2 Timing (24bit, MSB justified)
MS1173-E-01
2010/09
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
