ASAHI KASEI
[AK4122]
96kHz Clock Recovery
The on-chip, low jitter PLL of DIR has a wide lock range of 32kHz to 96kHz and a lock time of less than 20ms. The
AK4122 has a sampling frequency detect function (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) that uses either clock
comparison against the MCLK2 or OMCLK frequency or the channel status information. The PLL loses lock when the
received sync interval is incorrect.
Biphase Input
Four receiver inputs (RX1-4) of DIR are available. Each input includes an amplifier for unbalance loads that can accept
200mVpp or greater signal. The IPS1-0 bits select the receiver channel (Table 14).
IPS1
IPS0
Input Data
RX1
Default
0
0
1
1
0
1
0
1
RX2
RX3
RX4
Table 14. Recovery Data Select
Biphase Output
The AK4122 can output the through data from the digital receiver inputs (RX1-4) to the TX pin. The OPS1-0 bits can
select the source of the output from the TX pin. TX output can be stopped by TXE bit. AK4122 does not have the TX
output buffer (Line Driver), the TX pin cannot drive the 75Ω coaxial cable directly.
OPS1
OPS0
Output Data
RX1
Default
0
0
1
1
0
1
0
1
RX2
RX3
RX4
Table 15. Output Data Select for TX
MS0267-E-02
2004/07
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AKM [ ASAHI KASEI MICROSYSTEMS ]
