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AK4122VQ 参数 Datasheet PDF下载

AK4122VQ图片预览
型号: AK4122VQ
PDF下载: 下载PDF文件 查看货源
内容描述: 24位96kHz的SRC与DIR [24-Bit 96kHz SRC with DIR]
分类和应用: 消费电路商用集成电路
文件页数/大小: 53 页 / 363 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4122]  
„ De-emphasis Filter Control  
The AK4122 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to three sampling  
frequencies (32kHz, 44.1kHz and 48kHz).  
(1) When input port is DIR  
When the input port is DIR and DEAU bit = “1”, the de-emphasis filter is enabled automatically by sampling frequency  
(FS3-0 bit) and pre-emphasis information in the channel status. DEM1-0 bits can control the de-emphasis filter when  
DEAU bit = “0”. When the de-emphasis filter is OFF, the internal de-emphasis filter is bypassed. When PEM bit = “0”,  
the internal de-emphasis filter is always bypassed.  
PEM  
FS3  
0
0
FS2  
0
0
FS1  
0
1
FS0  
0
0
Mode  
44.1kHz  
48kHz  
32kHz  
OFF  
1
1
1
1
0
0
0
1
1
(Others)  
x
x
x
x
OFF  
Table 11. De-emphasis Auto Control (DEAU bit = “1”)  
PEM  
DEM1  
DEM0  
Mode  
44.1kHz  
OFF  
48kHz  
32kHz  
1
1
1
1
0
0
1
1
0
1
0
1
Default  
Table 12. De-emphasis Manual Control (DEAU bit = “0”)  
(2) When input port is PORT1 or PORT2  
When PORT1 or PORT2 is selected as input port, DEM1-0 bits can control the de-emphasis filter even if DEAU bit = “0”  
or DEAU bit = “1”. In this case, the de-emphasis filter cannot enable automatically. When the de-emphasis filter is OFF,  
the internal de-emphasis filter is bypassed.  
DEM1  
DEM0  
Mode  
44.1kHz  
OFF  
48kHz  
32kHz  
0
0
1
1
0
1
0
1
Default  
Table 13. De-emphasis Manual Control  
„ System Reset and Power-Down  
The AK4122 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down mode  
activated by the PWN bit. The AK4122 should be reset once at power-up by bringing PDN pin = “L”.  
PDN pin:  
All analog and digital circuits are placed in power-down and reset modes by bringing PDN pin = “L”. All the  
registers are initialized and clocks are stopped. Read/Write operations to the registers are disabled.  
PWN bit (Address 00H; D0):  
Unlike the PDN pin operation described above, internal registers and mode settings are not initialized. Read/Write  
operations to the registers are enabled.  
MS0267-E-02  
2004/07  
- 23 -  
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