ASAHI KASEI
[AK4122]
Interrupt Handling for DIR
There are nine events that cause the INT2-0 pins to go “H”.
1. UNLCK: PLL unlock state detection
“1” when the PLL loses lock. The AK4122 loses lock when the distance between two preambles is
not correct or when those preambles are not correct.
2. PAR:
3. AUTO:
4. V:
Parity error or biphase coding error detection
“1” when parity error or biphase coding error is detected, updated every sub-frame cycle.
Non-PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is output to the AUTO bit.
Validity flag detection
“1” when validity flag is detected. Updated every sub-frame cycle.
5. AUDN: Non-audio detection
“1” when the “AUDN” bit in recovered channel status indicates “1”. Updated every block cycle.
6. STC:
Sampling frequency or pre-emphasis information change detection
“1” when FS3-0 or PEM bit changes. Reading 07H register resets it.
7. QINT:
U bit (Q-subcode) sync flag
“1” when the Q-subcode differs from old one, and stays “1” until this register is read. Updated every
sync code cycle for Q-subcode. Reading 07H register resets it.
8. CINT:
9. DAT:
Channel status sync flag
“1” when received C bits differ from old ones, and stays “1” until this register is read. Updated every
block cycle. Reading 07H register resets it.
DAT Start ID detection
When the category code shows DAT, “1” when the Start ID of DAT is detected. Reading 08H register
resets it.
INT1-0 pins output an OR’ed signal based on the above nine interrupt events. When masked, the interrupt event does not
affect the operation of the INT1-0 pins (the masks do not affect the registers (UNLCK, PAR, etc.) themselves). Once
INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events not
masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared.
INT2 pin output a state change on the above 1 ∼ 5 and an OR’ed signal based on the above 6 ∼ 9. It stays “H” until 07H
and 08H registers are read. Mask bits are shared with INT0.
UNLCK, AUTO, V and AUDN bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or
CINT and DAT bit goes to “1”, it stays “1” until the register is read.
When the AK4122 loses lock, the channel status bits are initialized. In this initial state, INT0 and INT2 outputs the OR’ed
signal between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDN. INT2-0 pins are “L”
when the DIR is not selected.
When DIR is used as input port and the PLL loses lock (unlock state), the output data is muted automatically. When
AMUTE bit = “1”, SDTIO and SDTO are muted automatically when the AK4122 detects unlock, Non-Audio or
Non-PCM/DTS-CD. After the interrupt events are cleared, mute is cancelled automatically. When AMUTE bit = “0”,
SDTIO and SDTO outputs “L” when the PLL loses lock (unlock state), and outputs data when other errors (PAR, AUTO
etc.).
MS0267-E-02
2004/07
- 28 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
