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AK4122VQ 参数 Datasheet PDF下载

AK4122VQ图片预览
型号: AK4122VQ
PDF下载: 下载PDF文件 查看货源
内容描述: 24位96kHz的SRC与DIR [24-Bit 96kHz SRC with DIR]
分类和应用: 消费电路商用集成电路
文件页数/大小: 53 页 / 363 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4122]  
„ Master Mode and Slave Mode  
When PORT2 and PORT3 are used as output port, the M/S2 pin and M/S3 pin select either master or slave mode. “H” is  
master mode, “L” is slave mode. In master mode, MCLK should be input and the AK4122 outputs BICK and LRCK. In  
slave mode, BICK and LRCK are input externally and MCLK is not needed. If PORT2 is used as input port, M/S2 pin  
should be set “H” or “L”.  
M/S2 pin  
L
BYPS bit  
0
Data I/O  
I/O  
Input  
Output  
I/O  
Mode  
Slave, SRC  
Available  
Not Available  
Master, SRC  
Master, Bypass  
BICK, LRCK  
Input  
L
1
H
H
0
1
Output  
I/O  
Table 6. Master mode/Slave mode for PORT2  
M/S3 pin  
BYPS bit  
Data I/O  
Output  
Output  
Output  
Output  
Mode  
Slave, SRC  
Not Available  
Master, SRC  
Master, Bypass  
BICK, LRCK  
Input  
L
L
H
H
0
1
0
1
Output  
Table 7. Master mode/Slave mode for PORT3  
„ Audio Interface Format  
The audio interface should be controlled during PWN bit = “0”. When in BYPASS mode, BICK1, BICK2 and BICK are  
fixed to 64fs.  
(1) PORT1  
Four kinds of data formats can be chosen with the DIF1-0 bits (Table 8). In all modes, the serial data is in MSB first, 2’s  
compliment format. The SDTI is latched on the rising edge of BICK1. PORT1 corresponds to slave mode only.  
Mode  
DIF1  
DIF0  
Input Format  
LRCK BICK  
0
1
2
3
0
0
1
1
0
1
0
1
16bit, LSB justified  
24bit, MSB justified  
24bit, I2S Compatible  
24bit, LSB justified  
H/L  
H/L  
L/H  
H/L  
32fs  
48fs  
48fs  
48fs  
Default  
Table 8. Audio Interface Format for PORT1  
Note: The DIF1-0 bits of the PORT1 should be set a value except “10” (I2S Compatible) when the DIR is  
selected as an input port.  
LRCK  
0
1
2
3
9 10 11 12 13 14 15 0  
1
2
3
9 10 11 12 13 14 15 0 1  
BICK(32fs)  
SDTI(i)  
15 14 13  
7
6
5
4
3
2
1
0 15 14 13  
7
6
5
4
3
2
2
1
0 15  
0
1
2
3
17 18 19 20  
31 0  
1
2
3
17 18 19 20  
31 0  
1
BICK(64fs)  
SDTI(i)  
Don't Care 15 14 13 12  
SDTI-15:MSB, 0:LSB  
1
0
Don't Care 15 14 13 12  
Rch Data  
1 0  
Lch Data  
Figure 2. Mode 0 Timing  
MS0267-E-02  
2004/07  
- 18 -  
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