ASAHI KASEI
[AK4122]
OPERATION OVERVIEW
Internal Signal Path
The input source of the SRC can be switched between the outputs of the DIR, PORT1 or PORT2. The input source of the
PORT2 and PORT3 can be switched between the outputs of the SRC or BYPASS. When PORT2 is used as input port,
PORT2 cannot use as output port. The signal path should be controlled during PWN bit = “0”. The Switch Names
(ISEL1-0 bits etc) in Figure 1 correspond to the register bits that control the switch function. Refer to Table 1.
DIR
PORT3
PORT1
Serial
Audio
I/F
OSEL
Serial
Audio
I/F
De-em
Filter
SRC
ISEL1-0
BYPS
PORT2
PLL
Serial
Audio
I/F
Figure 1. Connection Input Source & Output Source
Input PORT
SRC / Bypass
BYPS bit
Output PORT
OSEL bit
Mode
Path
ISEL1-0 bit
00 : PORT1
01 : PORT2
10 : DIR
00 : PORT1
01 : PORT2
10 : DIR
0
1
2
3
4
5
6
7
8
9
PORT1 → SRC → PORT3
PORT2 → SRC → PORT3
DIR → SRC → PORT3
PORT1 → PORT3
PORT2 → PORT3
DIR → PORT3
PORT1 → SRC → PORT2
DIR → SRC → PORT2
PORT1 → PORT2
0 : SRC
0 : PORT3
(Note 1)
1 : Bypass
00 : PORT1
10 : DIR
00 : PORT1
10 : DIR
0 : SRC
1 : PORT2
(Note 2)
1 : Bypass
DIR → PORT2
Table 1. Path Select
Default is Mode 0. (Path : PORT1 → SRC → PORT3)
After PDN pin = “L” → “H”, SDTIO pin of PORT2 is the input pin.
The DIF1-0 bits of the PORT1 should be set a value except “10” (I2S Compatible) when the DIR is
selected as an input port.
Refer to Table 6 and 7 for Master/Slave mode setting.
MS0267-E-02
2004/07
- 16 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
