[AK4118]
SWITCHING CHARACTERISTICS (Continued)
(Ta=25°C; DVDD=AVDD2.7~3.6V, TVDD=2.7~5.5V; C
L
=20pF)
Parameter
Symbol
min
typ
2
Control Interface Timing (I C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
8)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
100
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive load on bus
Cb
-
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Reset Timing
PDN Pulse Width
tPW
150
Note 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 9. I
2
C is a registered trademark of Philips Semiconductors.
max
400
-
-
-
-
-
-
-
300
300
-
400
50
Units
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
pF
ns
ns
MS1042-E-01
-8-
2009/02
AKM [ ASAHI KASEI MICROSYSTEMS ]
