[AK4118]
■
Timing Diagram
1/fECLK
VIH
VIL
tECLKH
tECLKL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
XTI
1/fMCK1
MCKO1
tMCKH1
tMCKL1
50%DVDD
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
MCKO2
tMCKH2
tMCKL2
50%DVDD
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
VIH
VIL
tLRH
tLRL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
LRCK
Figure 1. Clock Timing
VIH
VIL
tBCK
tBLR
BICK
tLRB
tBCKL
tBCKH
VIH
VIL
tLRM
tBSD
50%DVDD
tDXS
tDXH
VIH
VIL
LRCK
SDTO
DAUX
Figure 2. Serial Interface Timing (Slave Mode)
MS1042-E-01
-9-
2009/02