[AK4118]
SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD=AVDD2.7~3.6V, TVDD=2.7~5.5V; C
L
=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
11.2896
External Clock
Frequency
6)
fECLK
8.192
Duty
dECLK
40
50
MCKO1 Output
Frequency
fMCK1
4.096
Duty
dMCK1
40
50
MCKO2 Output
Frequency
fMCK2
2.048
Duty
dMCK2
40
50
PLL Clock Recover Frequency (RX0-7)
Fpll
8
-
LRCK Frequency
fs
8
Duty Cycle
dLCK
45
Audio Interface Timing
Slave Mode
BICK Period
tBCK
80
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
tLRB
20
LRCK Edge to BICK “↑”
7)
tBLR
20
BICK “↑” to LRCK Edge
7)
tLRM
LRCK to SDTO (MSB)
tBSD
BICK “↓” to SDTO
tDXH
20
DAUX Hold Time
tDXS
20
DAUX Setup Time
Master Mode
BICK Frequency
fBCK
64fs
BICK Duty
dBCK
50
tMBLR
-20
BICK “↓” to LRCK
tBSD
-15
BICK “↓” to SDTO
tDXH
20
DAUX Hold Time
tDXS
20
DAUX Setup Time
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
150
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
Note 6. When fECLK=8.192MHz, sampling frequency detect function (page16) is disable.
Note 7. BICK rising edge must not occur at the same time as LRCK edge.
max
24.576
24.576
60
24.576
60
24.576
60
192
192
55
Units
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
20
15
45
70
MS1042-E-01
-7-
2009/02
AKM [ ASAHI KASEI MICROSYSTEMS ]
