[AK4118]
PIN/FUNCTION (Continued)
No.
25
26
27
28
29
30
Pin Name
SDTO
BICK
MCKO2
DAUX
XTO
XTI
I/O
O
I/O
O
I
O
I
Function
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Master Clock Output 2 Pin
Auxiliary Audio Data Input Pin
X'tal Output Pin
X'tal Input Pin
Power-Down Mode Pin
31
PDN
I
When “L”, the AK4118 is powered-down, and all output pins go to “L” and
registers are initialized.
CM0
I
Master Clock Operation Mode 1 Pin in Parallel Mode
32
CDTO
O
Control Data Input Pin in Serial Mode, IIC= “L”.
CAD1
I
Control Data Pin in Serial Mode, IIC= “H”.
CM1
I
Master Clock Operation Mode 1 Pin in Parallel Mode
33
CDTI
I
Control Data Input Pin in Serial Mode, IIC= “L”.
SDA
I/O
Control Data Pin in Serial Mode, IIC= “H”.
OCKS1
I
Output Clock Select 1 Pin in Parallel Mode
34
CCLK
I
Control Data Clock Pin in Serial Mode, IIC= “L”
SCL
I
Control Data Clock Pin in Serial Mode, IIC= “H”
OCKS0
I
Output Clock Select 0 Pin in Parallel Mode
35
CSN
I
Chip Select Pin in Serial Mode, IIC=”L”.
CAD0
I
Chip Address 0 Pin in Serial Mode, IIC= “H”.
36
INT0
O
Interrupt 0 Pin
37
INT1
O
Interrupt 1 Pin
38
AVDD
I
Analog Power Supply Pin, 2.7V ~ 3.6V
External Resistor Pin
39
R
-
10kΩ +/-1% resistor should be connected to VSS3 externally.
Common Voltage Output Pin
40
VCOM
-
0.47µF capacitor should be connected to VSS3 externally.
41
VSS3
I
Ground Pin
Receiver Channel 0 Pin (Internal biased pin)
42
RX0
I
This channel is default in serial mode.
No Connect
43
NC
I
No internal bonding. This pin should be connected to VSS3.
44
RX1
I
Receiver Channel 1 Pin (Internal biased pin)
TEST 1 pin.
45
TEST1
I
This pin should be connected to VSS3.
46
RX2
I
Receiver Channel 2 Pin (Internal biased pin)
47
VSS4
I
Ground Pin
48
RX3
I
eceiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins (RX0-7 pins)should not be left floating.
MS1042-E-01
-5-
2009/02
AKM [ ASAHI KASEI MICROSYSTEMS ]
