ASAHI KASEI
[AK4115]
D0
Mask Control for INT0
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
04H INT0 MASK
MQIT0 MAUT0 MCIT0 MULK0 MVRX0 MSTC0 MAUD0 MPAR0
R/W
Default
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
MPAR0: Mask enable for PAR bit
0: Mask disable (Default)
1: Mask enable
MAUD0:Mask enable for AUDION bit
0: Mask disable
1: Mask enable (Default)
MSTC0: Mask enable for STC bit
0: Mask disable
1: Mask enable (Default)
MVRX0:Mask enable for VRX bit
0: Mask disable
1: Mask enable (Default)
MULK0:Mask enable for UNLCK bit
0: Mask disable (Default)
1: Mask enable
MCIT0: Mask enable for CINT bit
0: Mask disable
1: Mask enable (Default)
MAUT0:Mask enable for AUTO bit
0: Mask disable
1: Mask enable (Default)
MQIT0: Mask enable for QINT bit
0: Mask disable
1: Mask enable (Default)
When mask is set to “1”, corresponding event does not affect INT0 pin operation.
MS0573-E-00
2006/12
- 51 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
