ASAHI KASEI
[AK2303LV]
Position of the Ch0,Ch1 PCM data in the DX/DR data flow
B1 and B2 channel of the PCM data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B
register. Time-slot on PCM High-way (Time-slot#0~31(MAX)) can be also assigned for B1 and B2 channel data
set as is defined by TS[4:0] register.
Channel selection
CH0,1selection(Address:100
Bit:6)
SEL2B
CH0
CH1
B2
Remarks
Default
on Reset
0
B1
1
B2
B1
PCM Interface
Analog Interface
Channe0
B1
B2
Channel 1
SEL2B
Time slot Assignment
B1, B2 Time-slot selection (Address:101
Bit:4~0)
TS[4:0]
Time slot
B1
B2
Remarks
The first half of 8bit
in Time-slot#0
The first half of 8bit
in Time-slot#XX
The first half of 8bit
in Time-slot#31
The latter half of
8bit in Time-slot#0
The latter half of
8bit in Time-slot#XX
The latter half of
Default
On Reset
00000
0
00001 to
11110
XX
31
11111
8bit in Time-slot#31
FS
TS#0
B2
TS#1
DR/X
TS#2
TS#3
TS#31(max)
Time slot#
ex)
Default
B1
B1
DR/X
ex)
B1
B2
TS[4:0]=2 setting
2303-E-00
10
2001/09
AKM [ ASAHI KASEI MICROSYSTEMS ]
