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AK2303LV 参数 Datasheet PDF下载

AK2303LV图片预览
型号: AK2303LV
PDF下载: 下载PDF文件 查看货源
内容描述: 双PCM编解码器的模拟PBX线卡 [Dual PCM CODEC for PBX Analog Line Card]
分类和应用: 解码器编解码器电信集成电路电信电路光电二极管PC
文件页数/大小: 41 页 / 560 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI
[AK2303LV]
PIN FUNCTION
Pin# Name
1
TEST
2
VFTN1
I/O
I
I
Function
TEST MODE setting (Please tie to AVSS)
0: Normal mode 1: Test mode
Negative analog input of the transmit OPamp(AMPT1) for channel 1.
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST1.
Output of the transmit OPamp(AMPT1) for channel 1.
Output of the receive OPamp(AMPR1) for channel 1.
Negative analog input of the receive OPamp(AMTR1) for channel 1.
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR1.
Analog Output equivalent to the received PCM data for channel 1.
A-law/u-law Select
0:A-law
1:u-law
Positive supply voltage for analog circuit.
+3.3V supply.
Positive supply voltage for digital circuit.
+3.3V supply.
Frame sync input.
FS must be 8kHz clock which is synchronized with BCLK.
Bit clock of PCM data interface.
This clock is input for the internal PLL which gerenates the internal system clocks.
This clock defines the input/output data rate of DX and DR.
The frequency of BCLK should be 2.048MHz or 4.096MHz set via CPU register..
Serial output of PCM data.
The channel 1 data is output following the channel 0 data. The PCM data rate is
synchronized with BCLK. This output remains in the high impedance state except for the
period of transmitting PCM data.
Serial input of PCM data.
The channel 1 data is received following the channel 0 data. The PCM data rate is
synchronized with BCLK.
CH1 mute setting
0:mute
1:normal operation
CH0 mute setting
0:mute
1:normal operation
Clock input of serial interface.
Data input of serial interface.
Read and write enable of serial interface.
Pin for PLL loop filter.
External capacitance(Min 0.22uF) should be connected between this pin and AVSS.
3
4
5
GST1
GSR1
VFR1
O
O
I
6
7
8
9
10
11
VR1
ALAWN
AVDD
DVDD
FS
BCLK
O
I
-
-
I
I
12
DX
O
13
DR
I
14
15
16
17
18
19
MUTE1
MUTE0
SCLK
DATA
CSN
LPC
I
I
I
I/O
I
O
2303-E-00
6
2001/09