ASAHI KASEI
[AK2303LV]
Long Frame
FS
BCLK
B1 ch
B2 ch
DX
DR
1
1
2
2
3
3
4
4
5
6
6
7
7
8
1
1
2
2
3
3
4
5
5
6
6
7
7
8
Don’t
care
Don’t care
5
8
4
8
SEL2B=0
SEL2B=1
B1-CHANNEL (CH0)
B1-CHANNEL (CH1)
B2-CHANNEL (CH1)
B2-CHANNEL (CH0)
Short Frame
FS
BCLK
B1 ch
B2 ch
DX
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
Don’t
care
Don’t care
DR
8
8
SEL2B=0
SEL2B=1
B1-CHANNEL (CH0)
B1-CHANNEL (CH1)
B2-CHANNEL (CH1)
B2-CHANNEL (CH0)
! Important Notice
Please set time-slot selection as proper value. Maximum time slot is determined from clock speed.
At the power up sequence, please set the mute by MUTE0/1 before power up.
Then release them after the CODEC initialization and TS assignment to avoid the PCM output data collision with other
CODEC’s PCM output.
Please don’t stop feeding FS and BCLK except in Full power down mode.
Internal PLL does free running when BCLK is not provided.
2303-E-00
11
2001/09
AKM [ ASAHI KASEI MICROSYSTEMS ]
