Operation
A block diagram of the HCTL-
20XX-XX family is shown in
Figure 10. The operation of
each major function is described
in the following sections.
Decode / Cascade
Outputs (Y)
U/DY
CNTDECY
CNTCASY
Decode / Cascade
Outputs (X)
U/DX
CNTDECX
CNTCASX
CLK
Digital Filter
4x/2x/1x
Decode Logic
Octal 4 bit
Mux/Buffer
32 Bits Binary
Counter
32 Bits Latch
8
QX0 - QX31
QY0 - QY31
DX0 - DX31
DY0 - DY31
D0 - D7
32
32
CHAX
8
8
CHAX filtered
DX0 - DX7
DX0 - DX7
DX8 - DX15
DX16 - DX23
DX24 - DX31
DY0 - DY7
DX8 - DX15
DX16 - DX23
DX24 - DX31
DY0 - DY7
CHBX
CNTX
UP/DN X
CNTY
CNTX
8
8
8
8
8
8
CHBX filtered
UP/DN X
CNTY
CHAY
CHAY filtered
DY8 - DY15
DY16 - DY23
DY24 - DY31
DY8 - DY15
DY16 - DY23
DY24 - DY31
UP/DN Y
UP/DN Y
CHBY
CHBY filtered
CLRX
CLRY
CHIX
SEL1
SEL2
CLRX
CHIX filtered
CLRY
CHIY
CHIY filtered
EN1
EN2
RX
RY
INHX INHY
OE
XNY
RSTX
RSTY
Inhibit Block
CLRX
EN1
CLRY
EN2
SEL1 SEL2 OE
SEL1
SEL2
OE
XNY
Figure 10. Simplified Logic Diagram
11
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