t RST
RSTX / RSTY
Figure 1. Reset Waveform
tCLK
tCHH
tCLH
CLK
tCD
DATA NOT STABLE
NEW
DATA
OLD
DATA
D0-D7
tDCD
tDCD
Figure 2: Waveforms for Positive Clock Edge Related Delays
tDOD
OE
tODE
tODZ
NOT STABLE
-
HIGH Z
-
NOT STABLE
STABLE DATA
HIGH
Z
D0-D7
Figure 3: Tri-State Output Timing
CLK
OE
tOS
tOH
tSH
SEL2
SEL1
tSS
tSDV
tSDV
tSDV
tSDV
INTERNAL
INHIBIT
tDSD
tDSD
tDSD
tDSD
2nd BYTE STABLE
HIGH -Z
D0-D7
HIGH - Z OR UNSTABLE DATA
MSB STABLE
3rd BYTE STABLE
LSB STABLE
Figure 4: Bus Control Timing
8