Position Data Latch
Bus Interface
held one clock cycle after the
rising edge of the CNT
pulse. These outputs are not
affected by the inhibit logic.
DCDR
The position data latch is a 32- The bus interface section
bit latch which captures the
position counter output data on
each rising clock edge, except
when its inputs are disabled by
the inhibit logic section during
four-byte read operations. The
consists of a 32 to 8 line
multiplexer and an 8-bit, three-
state output buffer. The
multiplexer allows independent
access to the low and high bytes
of the position data latch. The
Cascade Output
(HCTL-2032 / 2032-SC only)
The cascade output also consists
of count and up/down outputs.
When the HCTL-2032 / 2032-SC
internal counter overflows or
underflows, a pulse, one-half
clock cycle long, will be output
output data is passed to the bus SEL1, SEL2 and OE signals
interface section. When active, a
signal from the inhibit logic
section prevents new data from
being captured by the latch,
keeping the data stable while
successive reads are made
through the bus section. The
latch is automatically re-enabled (HCTL-2032 / 2032-SC only)
at the end of these reads. The
latch is cleared to 0
determine which byte is output
and whether or not the output
bus is in the high-Z state. In
the HCTL-20XX-XX, the data
latch is 32 bit wide.
on the CNT
pin. This output
CAS
will occur during the clock cycle
in which the internal counter is
updated. The U/D pin will be
set to the proper voltage level
one clock cycle before the rising
Quadrature Decoder Output
The quadrature decoder output
section consists of count and
up/down outputs derived from
the 4x/2x/1x decoder mode of
the HCTL-2032 / 2032-SC.
When the decoder has detected
a count, a pulse, one-half clock
cycle long, will be output on the
asynchronously by the RST
signal.
edge of the CNT
pulse, and
CAS
held one clock cycle after the
rising edge of the CNT pulse.
CAS
Inhibit Logic
These outputs are not affected
by the inhibit logic.
The Inhibit Logic Section
samples the OE, SEL1 and SEL2
signals on the falling edge of
the clock and, in response to
certain conditions (see Figure
15), inhibits the position data
latch. The RST signal
CNT
pin. This output will
DCDR
occur during the clock cycle in
which the internal counter is
updated. The U/D pin will be
set to the proper voltage level
one clock cycle before the rising
asynchronously clears the
inhibit logic, enabling the latch. edge of the CNT
pulse, and
DCDR
Step
SEL1
SEL2
OE
CLK
Inhibit Signal Action
1
L
H
L
1
1
1
1
0
Set inhibit; Read MSB
nd
2
3
4
5
H
L
H
L
L
L
L
H
Read 2 Byte
rd
Read 3 Byte
H
X
L
Read LSB
X
Completes inhibit logic reset
Figure 15. Four Bytes Read Sequence
15
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
