Digital Noise Filter
Figure 11 shows the simplified
schematic of the input section.
The signals are first passed
through a Schmitt-trigger buffer
to address the problem of input
signals with slow rise times and
low-level noise (approximately <
1V). The cleaned up signals are
then passed to a four-bit delay
filter. The signals on each
channel are sampled on rising
clock edges. A time history of
the signals is stored in the four-
bit shift register. Any change on
the input is tested for a stable
level being present for three
consecutive rising clock edges.
Therefore, the filtered output
waveforms can change only
after an input level has the
same value for three consecutive
rising clock edges.
The digital noise filter section is
responsible for rejecting noise
on the incoming quadrature
signals. The input section uses
two techniques to implement
improved noise rejection.
Schmitt-trigger inputs and a
three-clock-cycle delay filter
combine to reject low level
noise and large, short duration
noise spikes that typically occur
in motor system applications.
Both common mode and
differential mode noise are
rejected. The user benefits from
these techniques by improved
integrity of the data in the
counter. False counts triggered
by noise are avoided.
Refer to Figure 12, which shows
the timing diagram. The result
of this circuitry is that short
noise spikes between rising
clock edges are ignored and
pulses shorter than two clock
periods are rejected.
CHA
filtered
J
Q
Q
Q
CK
CK
CK
K
CHA
D
D
D
Q
Q
Q
D
D
D
Q
Q
Q
D
D
D
Q
Q
Q
D
D
D
Q
Q
Q
CK
CHB
filtered
J
K
CHB
CK
CHI
filtered
J
K
CHI
CK
Figure 11. Simplified Digital Noise Filter Logic
12
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