Switching Characteristics
Table 5. Switching Characteristics
O
Max/Min specifications at V = 5.0 ± 5%, T = -40 to +100 C, C = 40 pf
DD
A
L
Symbol Description
Min.
Max.
Units
MHz
ns
1
2
3
t
t
t
Clock Period
33
CLK
CHH
CD
Pulse width, clock high
1/f
Delay time, rising edge of clock to valid, updated count information on
D0-7
31
ns
4
5
6
t
t
t
Delay time, OEN fall to valid data
29
29
29
ns
ns
ns
ODE
ODZ
SDV
Delay time, OEN rise to Hi-Z state on D0-7
Delay time, SEL0~SEL1 valid to stable, selected data byte (delay to
High Byte = delay to Low Byte)
7
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, XNY valid to stable, selected data byte.
Pulse width, clock low
29
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XNYDV
CLH
8
15
9
Setup time, SEL1~SEL2 before clock fall
12
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Setup time, OEN before clock fall
12
OS
Setup time, XNY before clock fall
12
XNYS
SH
Hold time, SEL1~SEL2 after clock fall
0
Hold time, OEN after clock fall
0
OH
Hold time, XNY after clock fall
0
XNYH
RST
Pulse width, RSTNX~RSTNY low
10
Hold time, last position count stable on D0-7 after clock rise
Hold time, last data byte stable after next SEL state change
Hold time, data byte stable after OEN rise
Hold time, data byte stable after XNY change
Delay time, U/DNX valid after clock rise
2
DCD
2
DSD
2
DOD
2
DXNYD
UDDX
UDDY
CHXD
CHYD
CLXD
CLYD
UDXH
UDYH
UDCXS
UDCYS
UDCXH
UDCYH
4
29
29
31
31
31
31
Delay time, U/DNY valid after clock rise
4
Delay time, CNTDECX or CNTCASX high after clock rise
Delay time, CNTDECY or CNTCASY high after clock rise
Delay time, CNTDECX or CNTCASX low after clock fall
Delay time, CNTDECY or CNTCASY low after clock fall
Hold time, U/DNX stable after clock rise
4
4
4
4
2
Hold time, U/DNY stable after clock rise
2
Setup time, U/DNX valid before CNTDECX or CNTCASX rise
Setup time, U/DNY valid before CNTDECY or CNTCASY rise
Hold time, U/DNX stable after CNTDECX or CNTCASX rise
Hold time, U/DNY stable after CNTDECY or CNTCASY: rise
Note 1
Note 1
Note 2
Note 2
31
Notes
1. tclk − max delay (item 20/21) + min delay (item 22/23)
2. tclk − max delay (item 22/23) + min delay (item 20/21)
7
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