T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
10 GCI+ Interface Module (continued)
10.7 GCI+ Register Set (continued)
Table 86. GCDCI: GCI Downstream (Transmit) C/I Data (0x34)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
DCI6
—
Bit 4
DCI5
—
Bit 3
DCI4
—
Bit 2
DCI3
—
Bit 1
DCI2
—
Bit 0
DCI1
—
GCDCI
R/W
RESET Default
0
0
Bit # Symbol
Name/Description
7—6
—
Reserved. Program to 0.
5—0 DCI[6:1] Downstream Command/Indication Code. The microcontroller writes the desired down-
stream (transmit) C/I code to this register. The code will be continuously transmitted until a new
code is written. The internal GCI controller will not read the new code from the GCDCI until the
current code has been transferred in at least two consecutive frames (see Section 10.4, C/I
Message Transfer).
Table 87. GCUCI: GCI Upstream (Receive) C/I Data (0x35)
Reg
R/W
Bit 7
—
Bit 6
—
Bit 5
UCI6
—
Bit 4
UCI5
—
Bit 3
UCI4
—
Bit 2
UCI3
—
Bit 1
UCI2
—
Bit 0
UCI1
—
GCUCI
R/W
RESET Default
0
0
Bit #
Symbol
Name/Description
7—6
—
Reserved. Program to 0.
5—0 UCI[6:1] Upstream Command/Indication Code. Validated upstream (receive) C/I codes are stored
here. The validation circuit employs a double last look criterion, i.e., a new code is transferred
to the GCUCI register only if it is different from the previously loaded value and is received in
two consecutive GCI frames. The UCIC interrupt bit provides an indication that a new vali-
dated byte has been received.
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Lucent Technologies Inc.
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