T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
■ GPAF1[GPAF1.(7:5)] register bits, when set, override
GPDIR[DIR1.(7:5)] and configure GPIO1.[7:5] as
input trigger sources for timers 2, 1, and 0 (for proper
timer operation, the microcontroller should also con-
figure the associated SFR register bit for each timer).
11 GPIO Ports
Three general-purpose input/output ports are available
on the T9000 device with each port being 8 bits wide.
For any port, each signal may be individually config-
ured as an input or as an output by proper program-
ming of registers GPDIR[0:2]. On reset, all ports are
configured as inputs.
■ GPAF1[GPAF2.3] register bit, when set, overrides
the GPDIR2[DIR2.3] register bit and configures
GPIO2.3 as a SYNCO output from the dc/dc module
(see Section 13, dc/dc Control Generator).
All GPIO signals have a weak pull-up resistor of
100 kΩ (nominal value). Unneeded GPIO signals
should be configured as inputs, and may be left uncon-
nected. If connected on the board, it is recommended
that they be tied to VDD to avoid power consumption.
■ GPAF1[GPAF2.2] register bit, when set, overrides
the GPDIR2[DIR2.2] register bit and configures
GPIO2.2 as the reference frame sync clock (FSC)
output as specified in Section 10, GCI+ Interface
Module.
Registers GPD[0:2] contain the value on the GPIO pin.
For GPIO pins configured as inputs, the microcontroller
accesses the port value by reading its corresponding
GPD register. For GPIO pins configured as outputs, the
microcontroller writes the desired value into its corre-
sponding GPD register.
■ GPAF1[GPAF2.1] register bit, when set, overrides
the GPDIR2[DIR2.1] register bit and configures
GPIO2.1 as the GCI bit clock (BCLK) output (as
specified in Section 10, GCI+ Interface Module).
■ GPAF1[GPRESET] provides a nonlatching software
reset of the GPIO module. It has the same effect as a
global reset or a global software reset.
GPIO0.[3:0] and GPIO1.[3:0] pins, when configured as
inputs (see registers GPDIR0 and GPDIR1), may also
be configured as level-activated or transition-activated
external interrupt sources for the microcontroller (see
registers GPPOL and GPLEI). Any of these eight exter-
nal interrupt sources may be masked by proper pro-
gramming of register GPIE. On module reset, all
interrupts are disabled. GPIO interrupt register (GPIR)
is cleared when read by the microcontroller.
■ DOCR[LT_NT] register bit, when set, ignores
GPDIR2[DIR2.6] and configures GPIO2.6 as the
input for 8 kHz master transmit clock (MTC) signal.
■ When the test pin (pin 43) is asserted, GPIO1.4 and
GPIO2.7 change their functions to USSP_E and
PTLB_S, respectively, as explained in Table 4.
All registers are read/write to allow read-modify-write
operations by the microcontroller. Transition activated
interrupt sources may be individually reset by writing a
1 to the associated bits of GPPOL register.
GPIO0.[3:0] and GPIO1.[3:0] pins, when configured as
inputs, present a Schmitt trigger buffer for better noise
immunity.
GPAF0 and GPAF1 registers define alternate functional
modes for some GPIO pins.
All GPIO port signals are TTL levels. Driving capability
is 6 mA for GPIO2.0 signal and 1 mA for all others.
■ GPAF0[GPAF0.(7:6)] register bits, when set, override
GPDIR0 [DIR0.(7:6)] and configure GPIO0.[7:6] as
the PWM 1 output.
Figure 20 summarizes features available for all GPIO
signals.
■ GPAF0[GPAF0.(5:4)] register bits, when set, override
GPDIR0[DIR0.(5:4)] and configure GPIO0.[5:4] as
PWM0 outputs.
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