T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
GCOF1[GTMODE] = 1. The downstream timer will be
started each time the transfer of a downstream monitor
byte is initiated. If the byte is not acknowledged within
four frames, the timer will expire and generate an abort
request. The upstream timer will be started upon the
detection of a new byte. If this byte is not confirmed by
the far end (because it did not detect identical bytes in
two consecutive frames—upstream RNR event) or the
byte cannot be transferred to the GCUMD register
(because the microcontroller has not yet read the previ-
ous byte—upstream RNR event), the timer will expire.
10 GCI+ Interface Module (continued)
10.3 GCI-NT Mode (GCCF[GMODE(1:0)] = 00)
(continued)
10.3.2 Monitor Message Transfer
For both GCI-NT and GCI-TE modes, the NTN man-
ages the monitor channel (MON) protocol as defined
by the GCI standard. In GCI-NT mode, monitor data
transfer occurs in time slot 2 (MON-0) using the A&E
bit pair in time slot 3. In GCI-TE mode, monitor data
transfer occurs in time slot 6 (MON-1) using the A&E
bit pair in time slot 7.
10.4 C/I Message Transfer
Monitor messages may be one or more bytes in length.
To transmit a single byte message downstream, the
microcontroller writes the monitor byte into the GCDML
register. Once this byte is internally loaded, the GCI-
controller asserts the interrupt bit GCIR[DMRDY] indi-
cating to the microcontroller that it is ready to accept a
new message to be transmitted. If the transmission is
successfully completed, the GCI controller asserts
interrupt bit GCIR[DMEOM]. Otherwise, if the transmis-
sion has been aborted, it will assert interrupt bit
GCIR(DMABRT). Downstream monitor message
aborts may occur as a consequence of an abort
request by the downstream device or an expiration of
the GCI controller downstream timer (if
For both GCI-NT and GCI-TE modes, the NTN man-
ages data transfer over the command/indication chan-
nel as defined by the GCI standard. In GCI-NT mode,
C/I data transfer occurs in the first 6 bits of time slot 3
(C/I-0). In GCI-TE mode, C/I data transfer occurs in the
first 6 bits of time slot 7 (C/I-1).
To transmit a downstream C/I code, the microcontroller
writes the code into the GCDCI register. This code will
be continuously transmitted until a new code is written
to GCDCI. The internal GCI controller will not read the
new code from GCDCI until the current code has been
transferred in at least two consecutive frames.
Upstream command/indication codes are first filtered
before they are transferred to the GCUCI register. A
double last look criterion is used to validate a new C/I
code, i.e., a new code is transferred to the GCUCI reg-
ister only if it is different from the previously loaded
value and is received in two consecutive GCI frames.
Whenever this happens, the GCIR[UCIC] interrupt is
asserted.
GCOF1[GTMODE] = 1).
Multibyte monitor messages operate in a similar man-
ner to single-byte messages, except that for an N-byte
message, bytes 1 to N – 1 are written into register
GCDMD, and the last monitor byte is written into regis-
ter GCDML. The interrupt bit GCIR[DMRDY] is used in
both cases to signify when new downstream data may
be written to either GCDMD or GCDML.
Upstream monitor bytes, when confirmed, are trans-
ferred to the GCUMD register. Interrupt bit
10.5 GCI+ Powerdown Mode
GCIR[UMRDY] is asserted to indicate a new monitor
byte has been successfully received. At the completion
of an upstream message, interrupt bit GCIR[UMEOM]
is asserted. If the upstream message is aborted, the
interrupt bit GCIR [UMABRT] is asserted. Upstream
monitor message aborts may occur as a consequence
of an implicit abort produced by an invalid upstream
A&E bit pair sequence (normally produced by the
downstream device) or an expiration of the GCI con-
troller upstream timer (if GCOF1[GTMODE] = 1).
The GCI+ may be placed in a powerdown mode by set-
ting GCCF[GRATE(1:0)] = 00). Prior to enabling power-
down mode, the user must set DFR[PFS1_ACT] = 0
and DFR[PFS2_ACT] = 0. While in powerdown mode,
the DCL clock signal is stopped (held low), the PFS1
and PFS2 signals are held low, and the DD signal is
3-stated.
When in powerdown, a falling edge on the DU signal
causes an assertion of the interrupt bit GCIR[GWUP].
This allows the user to write a powerup routine for the
GCI+ interface.
The embedded GCI controller has one timer associ-
ated with each monitor direction to avoid deadlock situ-
ations. Both timers may be enabled by setting
Lucent Technologies Inc.
77
AGERE [ AGERE SYSTEMS ]
