T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
10.3 GCI-NT Mode (GCCF[GMODE(1:0)] = 00)
10 GCI+ Interface Module (continued)
Figure 16 shows the frame structure for the GCI-NT
mode. The DCL clock rate is automatically set to
512 kHz, overriding the value defined by
GCCF[GRATE(1:0)]. In addition, a powerdown mode is
available in which DCL is stopped (see Section 10.5,
GCI+ Powerdown Mode).
10.2 GCI Modes (GCCF[GMODE(1:0)] = 0x)
GCI mode is for use with codecs having a GCI inter-
face. Two GCI modes are supported by the NTN
device:
■ GCI-NT mode with a GCI frame structure of only one
The data rate in GCI-NT mode is automatically set to
256 kHz, overriding the value defined by
GCCF[CKMODE]. A total of four 8-bit time slots are
contained in each frame. Time slots 0 and 1 carry user
data, time slot 2 is the GCI monitor (MON) channel,
and time slot 3 is the GCI signaling and control chan-
nel.
GCI channel.
■ GCI-SCIT mode with a GCI frame structure of three
GCI channels.
In both modes, the circuit operates as a GCI master
device, i.e., the DCL output pin provides the GCI clock
signal (512 kHz or 1536 kHz). A BCLK signal is avail-
able on the GPIO2.1 pin when GPAF1[GPAF2.1] = 1.
BCLK occurs once per bit time and is a divide-by-two
version of the DCL signal.
The FS1 output pin provides the frame synchronization
clock (FSC) as defined by the GCI standard. It
becomes active with the rising edge of DCL at the start
of time slot 0 and is turned off one-half of a DCL period
prior to the start of time slot 1.
The FS1 output pin provides the frame synchronization
clock (FSC) signal as defined by the GCI standard (see
Figure 17). The internal PFS1 and PFS2 signals mark
the location of the B1 and B2 time slots on the TDM
highway. PFS2 is output on the FS2 pin (see Table 77).
PFS1 can be made available on the GPIO2.2 pin by
setting GPAF1[GPAF2.2] = 1.
In this mode, the NTN device:
■ May transfer upstream/downstream data on time-
slots 0 and 1.
■ Manages the MON channel’s operation, mainte-
nance, and data transfer (see Section 10.3.2, Moni-
tor Message Transfer for more details).
The PFS1 and PFS2 (programmable frame sync) sig-
nals may be programmed to be a pulse (duration of
one bit period, sometimes referred to as short frame
sync) or envelope (duration of one time slot, some-
times referred to as long frame sync). Register bit
GCCF[PFSPE] sets the short or long frame sync mode.
■ Provides control of the C/I subchannel (see Section
10.4, C/I Message Transfer for more details).
Register bit GCOF1[OFF10] controls the time slots to
which PFS1 and PFS2 are associated. If
The U-interface B1 and B2 channels are normally
transferred to/from the codec on the time slots marked
by PFS1 and PFS2, respectively. This ordering can be
switched by setting the DFAC[BSWAP] register bit to 1.
GCOF1[OFF10] = 0 PFS1 occurs during time slot 0
(GCI-B1 channel) and PFS2 occurs during time slot 1
(GCI-B2 channel). If GCOF1[OFF10] = 1 the associa-
tion is reversed, PFS1 occurs during time slot 1
(GCI-B2 channel) and the PFS2 occurs during time slot
0 (GCI-B1 channel). Note that the GCOF1(OFF1[4:1])
bits are ignored in GCI-NT mode, as is the entire
GCOF2 register.
Register bit GCCF[PFSDEL] controls the relative
delay between PFSx (x = 1 or x = 2) and the first
data bit of the time slot associated with PFSx. When
GCCF[PFSDEL] = 0, the PFSx rising edge is coinci-
dent with the start of the first data bit of the correspond-
ing time slot. When GCCF[PFSDEL] = 1, the PFSx
rising edge occurs one data bit prior to the first data bit
of the corresponding time slot.
Generation of the PFSx signals and data transfer
to/from the corresponding time slots may be disabled
by setting DFR[PFSx_ACT] = 0.
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